The invention lies in the semiconductor technology field. More specifically, the invention relates to a method of operating a semiconductor memory, in which data values are written to the memory cells of the semiconductor memory. The invention also relates to a semiconductor memory that is suitable for being operated by the method.
Semiconductor memories, in particular semiconductor memories having dynamic memory cells comprising a selection transistor and a storage capacitor, are constructed in a matrix-like manner. They comprise word lines running in one direction and bit lines running transversely with respect thereto. Memory cells are activated by activation of the word lines, and data values are read in and out via the bit lines and sense amplifiers connected thereto. A word line decoder selects at least one of the word lines for activation in dependence on a word line address. A bit line decoder selects the bit line to be read, so that a memory cell arranged at a crossover between word line and bit line can be individually addressed.
For testing the semiconductor memory, data values representing a predetermined test pattern are written to the semiconductor memory. Afterward, the written-in data are read out again and compared with the written-in value by the test system. If a deviation is ascertained, a functional error is present, for example within the memory cell, the word line, the bit line or the corresponding decoders or even at some other location. In order to be able to test all of the memory cells sufficiently thoroughly according to different criteria, it is necessary for the memory cell array to be written to and read from a number of times. Given the multiplicity of memory cells in present-day semiconductor memories, by way of example semiconductor memories with 256 Mbit dynamic memory cells are available nowadays, just the process of writing to and reading from the memory cells takes up a not inconsiderable time. In order to reduce the test time, endeavors are made to carry out the process of writing predetermined data values to the memory cells as quickly as possible.
Semiconductor memories nowadays have a burst mode. This means that after the application of a start address, a number of memory cells prescribed by the burst length is automatically read. In the case of a cell array with n word lines and m addresses for the selection of bit lines, a number of n*m/burst length write accesses are necessary in order to write to the cell array in its entirety. The duration for writing to the semiconductor memory is therefore essentially determined by the memory size n*m.
It is accordingly an object of the invention to provide a semiconductor memory and a method of operating a semiconductor memory which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows the memory cells to be written to as quickly as possible. A further object of the invention is to specify a semiconductor memory which is particularly suitable for carrying out the method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a novel method of operating a semiconductor memory, wherein the semiconductor memory comprises:
a memory cell array having memory cells for selectively storing a first logic value and a second logic value, word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines;
a decoder for simultaneously selecting of one or a plurality of the word lines;
a voltage generator connected to the bit lines, for applying a predetermined voltage level to the bit lines;
and the method includes the steps of:
carrying out a potential equalization of in each case two bit lines;
subsequently bringing the bit lines to a level representing the first logic value or the second logic value; and
subsequently selecting a multiplicity of the word lines and writing the levels applied to the bit lines to the memory cells connected to the selected word lines.
In other words, he invention proposes a method for operating a semiconductor memory, the semiconductor memory comprising: a memory cell array having memory cells in order to store a first or a second logic value, having word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines, a decoder for the simultaneous selection of one or a plurality of the word lines, a voltage generator, to which the bit lines are connected in order to apply a predetermined level to the bit lines, and the method comprising the following steps: a potential equalization of in each case two bit lines is carried out, after the conclusion of the potential equalization, the bit lines are brought to a level representing the first or the second logic value, afterward, a multiplicity of the word lines is selected and the levels applied to the bit lines are written to the memory cells connected to the selected word lines.
With the above and other objects in view there is also provided, in accordance with the invention, a semiconductor memory that comprises: a memory cell array having memory cells in order to store a first or a second logic value, having word lines and bit lines, each of the memory cells being connected to one of the word lines and one of the bit lines, a decoder for the simultaneous selection of one or a plurality of the word lines, a voltage generator in order to apply a predetermined level to the bit lines, the voltage generator being designed to generate, on the output side, a level representing the first logic value, a level representing the second logic value, or an equalization level lying between these levels.
The invention is particularly suitable for preallocating a constant logic value, for example xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, to the entire memory cell array or at least selected portions of the memory cell array. For this purpose, after the application of the equalization level VBLEQ that biases the bit lines, via the same circuit path, either the level representing the logic xe2x80x9c0xe2x80x9d or the level representing the logic xe2x80x9c1xe2x80x9d is applied to the bit lines. The word lines are activated, so that the storage capacitor is connected to the respective bit lines. The levels applied to the bit lines are then written to the memory cells. All the word lines connected to the respective word line decoder can be activated, so that, in this way, a logic xe2x80x9c0xe2x80x9d or alternatively a logic xe2x80x9c1xe2x80x9d is written to the entire memory cell array including all the memory cells. Since the data values are not written to the memory cells via the conventional read-in path, but rather by additional circuit measures, this operation is designated as physical writing-in of a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
It is also possible for only one portion of the word lines connected to the word line decoder to be activated, so that the respective data values are written only to those memory cells which are connected to this portion of the word lines. In an advantageous manner, xe2x80x9c0xe2x80x9d, for example, may be written to the memory cells which are connected to said first portion of the word lines, while by contrast the opposite data value, for example xe2x80x9c1xe2x80x9d, may be written to the memory cells which are connected to the other, complementary portion of the word lines. In an expedient manner, a logic xe2x80x9c0xe2x80x9d is written to the memory cells connected to one of the word lines, while a logic xe2x80x9c1xe2x80x9d is written to the memory cells connected to the directly adjacent word line. This principle is continued such that a logic xe2x80x9c0xe2x80x9d is again written to the memory cells of the next word line in turn arranged directly adjacent. In this way, it is possible for the memory cell array to be preallocated the data values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d in a stripwise manner. If the strip-type writing-in is considered as described above, then there are situated between the memory cells of two word lines which are preallocated one of the data values the memory-cells of a further word line which are preallocated the complementary data value.
In the case of the conventional read-in path, data values are provided at sense amplifiers which correspondingly modulate the bit lines, so that afterward the memory cells are correspondingly written to. In contrast to this, the invention is not attached to the sense amplifier. The sense amplifier is even switched off in order not to influence the bit line. Rather, the voltage generator previously providing the equalization voltage VBLEQ lying between the level values representing a logic xe2x80x9c0xe2x80x9d and a logic xe2x80x9c1xe2x80x9d, in particular in the center thereof, is modified. This voltage generator is extended to the effect that it can also supply a logic xe2x80x9c0xe2x80x9d as well as a logic xe2x80x9c1xe2x80x9d. The level for the logic value xe2x80x9c0xe2x80x9d is at ground potential VSS. The level for the logic value xe2x80x9c1xe2x80x9d lies between the positive supply voltage and the equalization level VBLEQ and is designated by VBLH. The relationship VBLH=2*VBLEQ holds true. As a result, all the bit lines of the memory cell array are preallocated either a logic xe2x80x9c0xe2x80x9d or a logic xe2x80x9c1xe2x80x9d. During this preallocation phase, the signal paths which connect the voltage generator to the bit lines remain switched on. By contrast, the sense amplifiers are switched off.
Each of the sense amplifiers is connected to a noninverted bit line, in whose memory cells the data values are stored in noninverted form. The same sense amplifier is additionally connected to an inverted bit line, in whose memory cells the data values are stored in inverted form. In the case of conventional writing of data, therefore, identical data values cannot be written simultaneously to the memory cells connected to an inverted and a noninverted bit line. By means of the invention, by contrast, in each case identical data values can be written to the entire memory cell array in one step.
The invention is particularly suitable for regularly writing predetermined data values to the memory cell array simply and quickly. Thus, the memory cell array can be preallocated in each case an identical data value or blockwise an identical data value or a strip-like pattern of values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d can be written in. This is advantageous particularly during the functional testing of a semiconductor memory. The written-in data values are subsequently read out again and compared with a desired value, namely the written-in data value. If a deviation between read-out value and desired value is ascertained, it can be concluded from this that an error is present at a location in the semiconductor memory which, if appropriate, must still be localized by further modified tests. The rapid preallocation of the entire memory cell array saves test time. In particular in the case of present-day memory sizes of 256 Mbit memory cells or more, the time saved is considerable compared with conventional reading-in of data values. As a result, the semiconductor memory can be produced more cost-effectively or the test time saved can be used for further test sequences which increase the test coverage and test reliability.
The functional sequences in the semiconductor memory are controlled by a superordinate control device, a so-called state machine. After application of a control command, the control device generates a predetermined sequence of different control signals which control all of the functional units which are required for the execution of the desired function. By way of example, the semiconductor memory is put into a suitable test mode. The control device is then preset such that, upon application of an activation command for one of the memory banks, all the memory cells of the memory bank are automatically preallocated.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for operating a semiconductor memory and a novel semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.